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semiconductor group 1 1.96 ? 1 048 576 words by 16-bit organization ? 0 to 70 c operating temperature ? performance: ? single + 5 v ( 10 %) supply ? low power dissipation max. 550 active mw (-50 version) max. 495 active mw (-60 version) max. 440 active mw (-70 version) 11 mw standby (ttl) 5.5. mw standby (mos) ? output unlatched at cycle end allows two-dimensional chip selection ? read, write, read-modify-write, cas -before-ras refresh, ras -only refresh, hidden refresh and self refresh ? fast page mode capability ? 2 cas / 1 we ? all inputs, outputs and clocks fully ttl-compatible ? 4096 refresh cycles/64 ms ? plastic package: p-soj-42-1 400 mil -50 -60 -70 t rac ras access time 50 60 70 ns t cac cas access time 13 15 20 ns t aa access time from address 25 30 35 ns t rc read/write cycle time 90 110 130 ns t pc fast page mode cycle time 35 40 45 ns 1m x 16-bit dynamic ram (4k-refresh) advanced information HYB5116160BSJ-50/-60/-70
semiconductor group 2 hyb 5116160bsj-50/-60/-70 1m x 16-dram the hyb 5116160bsj is a 16 mbit dynamic ram organized as 1 048 576 words by 16 bits. the hyb 5116160bsj utilizes a submicron cmos silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. multiplexed address inputs permit the hyb 5116160bsj to be packaged in a standard soj 42 400 mil plastic package. these packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. system-oriented features include single + 5 v ( 10 %) power supply, direct interfacing with high-performance logic device families such as schottky ttl. ordering information pin names type ordering code package descriptions hyb 5116160bsj-50 on request p-soj-42-1 400 mil dram (access time 50 ns) hyb 5116160bsj-60 on request p-soj-42-1 400 mil dram (access time 60 ns) hyb 5116160bsj-70 on request p-soj-42-1 400 mil dram (access time 70 ns) a0 to a11 row address inputs a0 to a7 column addess inputs ras row address strobe oe output enable i/o1-i/o16 data input/output ucas upper column address strobe lcas lower column address strobe we read/write input v cc power supply (+ 5 v) v ss ground (0 v) n.c. not connected
semiconductor group 3 hyb 5116160bsj-50/-60/-70 1m x 16-dram pin configuration truth table ras lcas ucas we oe i/o1-i/o8 i/o9-i/o16 operation h l l l l l l l l h h l h l l h l l h h h l l h l l l h h h h h l l l h h h l l l h h h h high-z high-z dout high-z dout din don't care din high-z high-z high-z high-z dout dout don't care din din high-z standby refresh lower byte read upper byte read word read lower byte write upper byte write word write nop p-soj-42 (400 mil) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 vcc i/o1 i/o2 i/o3 i/o4 vcc i/o5 i/o6 i/o7 i/o8 n.c. n.c. we ras a11 a10 a0 a1 a2 a3 vcc 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 vss i/o16 i/o15 i/o14 i/o13 vss i/o12 i/o11 i/o10 i/o9 n.c. lcas ucas oe a9 a8 a7 a6 a5 a4 vss
semiconductor group 4 hyb 5116160bsj-50/-60/-70 1m x 16-dram no. 2 clock generator column address buffer(8) refresh controller refresh counter (12) address buffers(12) row no. 1 clock generator & data in buffer data out buffer column decoder sense amplifier i/o gating memory array 4096x256x16 row decoder a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 we ucas 4096 256 x16 . ras 8 12 16 i/o1 i /o2 oe 12 12 a10 a11 16 16 8 i /o16 lcas . voltage down generator vcc vcc (internal) block diagram
semiconductor group 5 hyb 5116160bsj-50/-60/-70 1m x 16-dram absolute maximum ratings operating temperature range ............................................................................................0 to 70 c storage temperature range.........................................................................................C 55 to 150 c input/output voltage ................................................................................-0.5 to min (vcc+0.5,7.0) v power supply voltage...................................................................................................-1.0v to 7.0 v power dissipation.............................................................................................................. ....... 1.0 w data out current (short circuit) ............................................................................................... . 50 ma note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics t a = 0 to 70 c, v ss = 0 v, v cc = 5 v 10 %, t t = 5 ns parameter symbol limit values unit test condition min. max. input high voltage v ih 2.4 vcc+0.5 v 1) input low voltage v il C 0.5 0.8 v 1) output high voltage ( i out = C 5 ma) v oh 2.4 C v 1) output low voltage ( i out = 4.2 ma) v ol C0.4v 1) input leakage current,any input (0 v v ih vcc + 0.3v, all other pins = 0 v) i i(l) C 10 10 m a 1) output leakage current (do is disabled, 0 v v out vcc + 0.3v) i o(l) C 10 10 m a 1) average v cc supply current: -50 ns version -60 ns version -70 ns version (ras , cas , address cycling, t rc = t rc min. ) i cc1 C C C 100 90 80 ma ma ma 2) 3) 4) 2) 3) 4) 2) 3) 4) standby v cc supply current (ras =cas = v ih ) i cc2 C2maC average v cc supply current, during ras -only refresh cycles: -50 ns version -60 ns version -70 ns version (ras cycling: cas = v ih , t rc = t rc min.) i cc3 C C C 100 90 80 ma ma ma 2) 4) 2) 4) 2) 4)
semiconductor group 6 hyb 5116160bsj-50/-60/-70 1m x 16-dram average v cc supply current, during fast page mode: -50 ns version -60 ns version -70 ns version (ras = v il , cas , address cycling, t pc = t pc min. ) i cc4 C C C 40 35 30 ma ma ma 2) 3) 4) 2) 3) 4) 2) 3) 4) standby v cc supply current (ras = cas = v cc C 0.2 v) i cc5 C1ma 1) average v cc supply current, during cas - before-ras refresh mode: -50 ns version -60 ns version -70 ns version (ras , cas cycling, t rc = t rc min.) i cc6 C C C 100 90 80 ma ma ma 2) 4) 2) 4) 2) 4) average self refresh current (cbr cycle with tras>trassmin., cas held low, we =vcc-0.2v, address and din=vcc-0.2v or 0.2v) i cc7 _1ma capacitance t a = 0 to 70 c, v cc = 5 v 10 %, f = 1 mhz parameter symbol limit values unit min. max. input capacitance (a0 to a11) c i1 C5pf input capacitance (ras , ucas , lcas , we , oe ) c i2 C7pf i/o capacitance (i/o1-i/o16) c io C7pf dc characteristics (contd) t a = 0 to 70 c, v ss = 0 v, v cc = 5 v 10 %, t t = 5 ns parameter symbol limit values unit test condition min. max.
semiconductor group 7 hyb 5116160bsj-50/-60/-70 1m x 16-dram ac characteristics 5)6) 16f t a = 0 to 70 c, v cc = 5 v 10 %, t t = 5 ns parameter symbol limit values unit note -50 -60 -70 min. max. min. max. min. max. common parameters random read or write cycle time t rc 90 C 110 C 130 C ns ras precharge time t rp 30 C 40 C 50 C ns ras pulse width t ras 50 10k 60 10k 70 10k ns cas pulse width t cas 13 10k 15 10k 20 10k ns row address setup time t asr 0C0C0Cns row address hold time t rah 8C10C10Cns column address setup time t asc 0C0C0Cns column address hold time t cah 10 C 15 C 15 C ns ras to cas delay time t rcd 18 37 20 45 20 50 ras to column address delay time t rad 13 25 15 30 15 35 ns ras hold time t rsh 13 15 C 20 C ns cas hold time t csh 50 60 C 70 C ns cas to ras precharge time t crp 5C5C5Cns transition time (rise and fall) t t 350350350ns7 refresh period t ref C64C64C64ms read cycle access time from ras t rac C50C60C70ns8, 9 access time from cas t cac C13C15C20ns8, 9 access time from column address t aa C25C30C35ns8,10 oe access time t oea C13C15C20ns column address to ras lead time t ral 25 C 30 C 35 C ns read command setup time t rcs 0C0C0Cns read command hold time t rch 0C0C0Cns11 read command hold time referenced to ras t rrh 0C0C0Cns11 cas to output in low-z t clz 0C0C0Cns8 output buffer turn-off delay t off 013015020ns12
semiconductor group 8 hyb 5116160bsj-50/-60/-70 1m x 16-dram output buffer turn-off delay from oe t oez 013015020ns12 data to oe low delay t dzo 0C0C0Cns13 cas high to data delay t cdd 13 C 15 C 20 C ns 14 oe high to data delay t odd 13 C 15 C 20 C ns 14 write cycle write command hold time t wch 8C10C10Cns write command pulse width t wp 8C10C10Cns write command setup time t wcs 0C0C0Cns15 write command to ras lead time t rwl 13 C 15 C 20 C ns write command to cas lead time t cwl 13 C 15 C 20 C ns data setup time t ds 0C0C0Cns16 data hold time t dh 10 C 10 C 15 C ns 16 data to cas low delay t dzc 0C0C0Cns13 read-modify-write cycle read-write cycle time t rwc 126 C 150 C 180 C ns ras to we delay time t rwd 68 C 80 C 95 C ns 15 cas to we delay time t cwd 31 C 35 C 45 C ns 15 column address to we delay time t awd 43 C 50 C 60 C ns 15 oe command hold time t oeh 13 C 15 C 20 C ns fast page mode cycle fast page mode cycle time t pc 35 C 40 C 45 C ns cas precharge time t cp 10 C 10 C 10 C ns access time from cas precharge t cpa C30C35C40ns7 ras pulse width t ras 50 200k 60 200k 70 200k ns cas precharge to ras delay t rhpc 30 C 35 C 40 C ns ac characteristics (contd) 5)6) 16f t a = 0 to 70 c, v cc = 5 v 10 %, t t = 5 ns parameter symbol limit values unit note -50 -60 -70 min. max. min. max. min. max.
semiconductor group 9 hyb 5116160bsj-50/-60/-70 1m x 16-dram fast page mode read-modify-write cycle fast page mode read-write cycle time t prwc 71 C 80 C 95 C ns cas precharge to we t cpwd 48 C 55 C 65 C ns cas -before-ras refresh cycle cas setup time t csr 10 C 10 C 10 C ns cas hold time t chr 10 C 10 C 10 C ns ras to cas precharge time t rpc 5C5C5Cns write to ras precharge time t wrp 10 C 10 C 10 C ns write hold time referenced to ras t wrh 10 C 10 C 10 C ns cas -before-ras counter test cycle cas precharge time t cpt 35 C 40 C 40 C ns self refresh cycle ras pulse width t rass 100k _ 100k _ 100k _ ns 17 ras precharge time t rps 95 _ 110 _ 130 _ ns 17 cas hold time t chs -50 _ -50 _ -50 _ ns 17 ac characteristics (contd) 5)6) 16f t a = 0 to 70 c, v cc = 5 v 10 %, t t = 5 ns parameter symbol limit values unit note -50 -60 -70 min. max. min. max. min. max.
semiconductor group 10 hyb 5116160bsj-50/-60/-70 1m x 16-dram notes: 1) all voltages are referenced to vss. 2) icc1, icc3, icc4 and icc6 depend on cycle rate. 3) icc1 and icc4 depend on output loading. specified values are measured with the output open. 4) address can be changed once or less while ras = vil. in the case of icc4 it can be changed once or less during a fast page mode cycle (tpc). 5) an initial pause of 200 m s is required after power-up followed by 8 ras cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas-before-ras initialization cycles instead of 8 ras cycles are required. 6) ac measurements assume tt = 5 ns. 7) vih (min.) and vil (max.) are reference levels for measuring timing of input signals. transition times are also measured between vih and vil. 8) measured with a load equivalent to 2 ttl loads and 100 pf. 9) operation within the trcd (max.) limit ensures that trac (max.) can be met. trcd (max.) is specified as a reference point only: if trcd is greater than the specified trcd (max.) limit, then access time is controlled by tcac. 10)operation within the trad (max.) limit ensures that trac (max.) can be met. trad (max.) is specified as a reference point only: if trad is greater than the specified trad (max.) limit, then access time is controlled by taa. 11)either trch or trrh must be satisfied for a read cycle. 12)toff (max.) and toez (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13)either tdzc or tdzo must be satisfied. 14)either tcdd or todd must be satisfied. 15)twcs, trwd, tcwd, tawd and tcpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if twcs > twcs (min.), the cycle is an early write cycle and the i/o pin will remain open-circuit (high impedance) through the entire cycle; if trwd > trwd (min.), tcwd > tcwd (min.), tawd > tawd (min.) and tcpwd > tcpwd (min.) , the cycle is a read-write cycle and i/o pins will contain data read from the selected cells. if neither of the above sets of conditions is satisfied, the condition of the i/o pins (at access time) is indeterminate. 16)these parameters are referenced to the cas leading edge in early write cycles and to the we leading edge in read-write cycles. 17)when using self refresh mode, the following refresh operations must be performed to ensure proper dram operation: if row addresses are being refreshed on an evenly distributed manner over the refresh interval using cbr refresh cycles, then only one cbr cycle must be performed immediately after exit from self refresh. if row addresses are being refreshed in any other manner (ror - distributed/burst; or cbr-burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from self refresh.
semiconductor group 11 hyb 5116160bsj-50/-60/-70 1m x 16-dram read cycle row address column address row address valid data out ras ucas address we oe i/o1-i/o16 (inputs) i/o1-i/o16 (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rc t csh t rad t cas t rp t rah t crp t rsh t rcd t ral t asr t cah t asc t asr t rch t rrh t rcs t aa t oea t clz t cac t oez t odd t cdd t off t dzc t dzo t rac hi z hi z h or l lcas
semiconductor group 12 hyb 5116160bsj-50/-60/-70 1m x 16-dram write cycle (early write) t cwl t rwl t wp t asc t wch valid data in t ds t dh hi z column address address row row address t rah t wcs h or l ras ucas address we oe i/o1-i/o16 (inputs) i/o1-i/o16 (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t rc t csh t rad t cas t rp t crp t rsh t rcd t ral t asr t cah t asr lcas
semiconductor group 13 hyb 5116160bsj-50/-60/-70 1m x 16-dram write cycle (oe controlled write) valid data t rwl t wp t oeh t odd t cwl t dzo t oea t clz t ds t oez t dh t rc v ih v il row address t dzc h or l hi-z hi-z column address address row t asc t rad t ral t cah t rah ras ucas address we oe i/o1-i/o16 (inputs) i/o1-i/o16 (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t csh t cas t rp t crp t rsh t rcd t asr t asr lcas
semiconductor group 14 hyb 5116160bsj-50/-60/-70 1m x 16-dram read-write (read-modify-write) cycle row address row address t csh t cas t crp t rwc t awd t asr t rp t ras t rah t cah i/o1-i/o16 (outputs) v oh v ol v ih v il v ih v il i/o1-i/o16 (inputs) oe we v ih v il t asr column address t rcd t dh t rsh t rad t cwd t oeh t rwd t rwl t cwl t clz t wp t rcs t aa t oea t ds t dzc t dzo t odd t cac t oez valid data in data out t rac h or l t asc v ih v il v ih v il ras ucas address v ih v il lcas
semiconductor group 15 hyb 5116160bsj-50/-60/-70 1m x 16-dram fast page mode read-modify-write cycle t cah t cp t dzc t dzo t rac t cac t clz t rcs t aa t oea t rcd t rad t rah t asr t asc t cas t cas t prwc t cwd t cah t asc t cas t rsh t rp t crp t asr t cah t asc t ral t cwd t rwd t cwl t cwl t cwd t awd t awd t wp t wp t cwl t rwl t awd t wp t odd t oeh t dh t ds t cpa t oez t clz t dzc t aa t cac t oea t ds t oez t dh t oeh t aa t odd t dzc t cpa t oea t clz t ds t dh t oeh t odd ras v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol we oe address (inputs) (outputs) data in data in data in data out out data data out address row column address address column address row address t rasp t csh column t cpwd t cpwd h or l i/o1-i/o16 i/o1-i/o16 ucas lcas
semiconductor group 16 hyb 5116160bsj-50/-60/-70 1m x 16-dram fast page mode read cycle t rasp t cas t cas t pc t cp t rcd t csh t cah t cah t asc t asc t asr t rah t rad t rcs t rcs t rcs t asc t cah t cas t rsh t crp t rp t asr t rch t cpa t oea t oea t aa t aa t dzc t dzc t cdd t rrh t cpa t oea t aa t dzc t dzo t odd t odd t dzo t odd t dzo t off t oez t oez t off t oez t cac t cac t clz t clz t clz t off t off t cac valid data out data out data out valid valid column address address addr address column row row ras i/o1-i/o16 (outputs) i/o1-i/o16 (inputs) oe we address v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il h or l t rhcp t rch v oh v ol column address ucas lcas
semiconductor group 17 hyb 5116160bsj-50/-60/-70 1m x 16-dram fast page mode early write cycle t rasp t rp t rsh t cas t cas t cp t crp t ral t cah t asr t cwl t rwl t cah t asc t asc t cwl t cwl t wcs t wcs t wcs t wch t wp t wp t wch t wp t wch t rad t cas t rcd t pc t cah t rah t asr t asc t dh t ds t ds t dh t dh t ds column address address address column column row addr valid data in valid valid data in data in column address hi-z ras i/o1-i/o16 (outputs) i/o1-i/o16 (inputs) oe we address v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il h or l v oh v ol ucas lcas
semiconductor group 18 hyb 5116160bsj-50/-60/-70 1m x 16-dram ras -only refresh cycle t crp t rah t rp t ras t rc t asr t asr t rpc v ih v il v ih v il v ih v il v oh v ol row address row address hi-z address ras i/o1-i/o16 (outputs) h or l ucas lcas
semiconductor group 19 hyb 5116160bsj-50/-60/-70 1m x 16-dram cas -before-ras refresh cycle t rp t ras t rp t rc t crp t cp t rpc t chr t wrh t wrp t csr t rpc t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z h or l ras i/o1-i/o16 (outputs) i/o1-i/o16 (inputs) oe we v oh v ol ucas lcas
semiconductor group 20 hyb 5116160bsj-50/-60/-70 1m x 16-dram hidden refresh cycle (read) ras i/o1-i/o16 (outputs) i/o1-i/o16 (inputs) oe we address t rc t rc t ras t ras t rp t rp t crp t chr t rad t cah t asc t rah t asr t asr t rcs t rrh t aa t dzc t dzo t cac t rac t clz t oez t off t odd t cdd t rcd t rsh t oea v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t wrp t wrh h or l valid data out row address column address row addr hi-z v oh v ol ucas lcas
semiconductor group 21 hyb 5116160bsj-50/-60/-70 1m x 16-dram hidden refresh cycle (early write) ras i/o1-i/o16 (output) i/o1-i/o16 (input) we address v ih v il v ih v il v ih v il ucas v ih v il v ih v il h or l t rc t ras t rcd t rsh t rad t cah t wcs t wch t wp t asr t rah t ds t dh t asr t crp t chr t rp t ras t rc t rp t asc address row addr row address valid data hi-z column v oh v ol t wrp t wrh lcas
semiconductor group 22 hyb 5116160bsj-50/-60/-70 1m x 16-dram cas before ras self refresh cycle t rps t rass t rp t crp t cp t rpc t wrh t wrp t csr t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z h or l ras i/o1-i/o16 (outputs) i/o1-i/o16 (inputs) oe we ucas v oh v ol t chs lcas
semiconductor group 23 hyb 5116160bsj-50/-60/-70 1m x 16-dram cas -before-ras refresh counter test cycle t csr t asr t asc t chr t cpt t wrp t ral t cah t rsh t rp t ras t cas t rcs t cdd t cac t aa t wrh t oea t odd t clz t dzc t dzo t oez t off t rwl t cwl t wch t wcs t wrh t wrp t ds t odd t dh t wrh t wrp t oez t rwl t cwl t awd t cwd t wp t rcs t cac t oea t oeh t aa t clz t dh t dzo t ds t dzc t cac v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il i/o1-i/o16 (inputs) ras i/o1-i/o16 (inputs) oe we address i/o1-i/o16 (outputs) i/o1-i/o16 (outputs) i/o1-i/o16 (inputs) we oe we oe i/o1-i/o16 (outputs) column address row address valid data out valid data in data in hi-z hi-z hi-z read cycle read-modify-write cycle write cycle t rrh t rch d.out ucas lcas
semiconductor group 24 hyb 5116160bsj-50/-60/-70 1m x 16-dram package outlines plastic package p-soj-42 (400 mil) (small outline j-lead, smd) index marking 1) does not include plastic or metal protusion of 0.15 max per side gpj05853 25.4 22 42x a 0.81 max. 42 0.18 1.27 0.43 1 27.43 21 a 0.08 11.2 9.4 0.18 b 10.3 b -0.3 1) -0.25 1) + - 0.1 + - 0.15 + - 0.25

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